The present invention relates to integrated circuit packages, and more specifically, to an improved vertical package for an integrated circuit.
A semiconductor device is typically packaged as a chip and mounted on a circuit board to mechanically and electrically connect the semiconductor device to the circuit board. This allows the semiconductor device to be electrically coupled to various other devices within a digital data processing system.
One known package type is a surface vertical package (xe2x80x9cSVPxe2x80x9d), which provides for the edge-mounting of chips to circuit boards. The semiconductor device is packaged in a relatively flat package such that the leads that provide for electrical connections to the semiconductor device are positioned on one edge of the chip. Typically a semiconductor die containing an integrated circuitxe2x80x94which can be a semiconductor memory, processor, or ASIC, for examplexe2x80x94resides in the center of a plastic package. Wires within the plastic package connect the semiconductor die with the leads, which reside on one end of the plastic package.
Each lead of the SVP chip is soldered to a respective solder pad on a circuit board to mechanically and electrically connect the semiconductor device to the circuit board. In the prior art, the leads of the SVP chip are bent substantially perpendicular relative to the SVP package so that the SVP chip is placed upright over the circuit board in soldering each lead to its respective solder pad. The SVP chip may have, at its bottom edge, supporting pins to help the SVP chip stand upright in soldering the SVP chip to the circuit board.
One problem with the prior SVP chip is that the electrical connection between the SVP chip and the circuit board is not of sufficiently high quality to handle extremely high frequencies and low voltage swings without electrical degradation.
Another disadvantage of the prior SVP chip is the difficulty in placing a large number of leads on one side of the SVP chip without having shorts between leads when the leads are soldered to the circuit board.
Another disadvantage of the prior SVP chip is that pressure applied to the SVP chip can lead to fractures in the leads, or short circuits, which in turn can lead to a loss of signal and a loss of data.
Another disadvantage of the prior SVP chip is the relative difficulty involved in installing and removing an SVP chip.
One object of the present invention is to provide for a mechanical and electrical connection of a chip to a circuit board which that results in less pressure being applied to the leads of the chip.
Another object of the present invention is to provide for a heat spreader and pressure plate as part of the chip package.
Another object of the present invention is to provide an integrated ground plane for the chip package.
Another object of the present invention is to provide for the capability for users to mechanically and electrically couple and decouple chips from a circuit board with relative ease.
Another object of the present invention is to provide for a relatively low inductance connection in mechanically and electrically coupling chips to a circuit board.
A chip package is described. The chip package includes a base and an integrated circuit, or chip. The chip package further includes a flex circuit containing a plurality of traces. The flex circuit is coupled to the base, and extends from a bottom of the base. The flex-circuit has a substantially J-shaped form. The integrated circuit is coupled to the traces of the flex circuit, and the traces of the flex circuit are coupled to traces on a printed circuit board.
Another chip package is also described. The chip package includes a base which is substantially J shaped. A conforming flex circuit is coupled to the base. An integrated circuit is placed on the flex circuit, and the leads of the integrated circuit are coupled to the traces in the flex circuit. The traces of the flex circuit are coupled to traces on a printed circuit board.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.